Heptane Central Processor Unit
The heptane computer processor is a project to create a very fast
computer processor in verilog harware description language,
which will
execute 9 instructions per clock cycle and will run at above 3GHz if implemented on a modern chip
process.
It will be designed with ease of translation to x86/x64 (R), and arm-7 (R) arhitectures with pointer
merged bounds checking instead of segmentation, which will allow porting 16 systems to 64 bit architecture.
It will be available for licensing once it's ready.
Check out more detailed description here:
ABOUT PROCESSOR
The heptane processor will now allow derrivative works.
Apache 2.0 License
Floating point unit completed.
As of sep 2021 the Heptane CPU is in the process of testing a whole core module by creating a random program and then running it and comparing the results (fuzzing).
The random program testing is paused right now;
You can get included in the NOTICE file as having a right to manufacture the core on the patreon membership.
Please bear in mind that this core is work in progress.
The code and data caches are now each 128 KB.
There is a linear search instruction for integer simd, which is new.
Support for "texture fetch" memory, where each lpddr5 channel can be fetched from separately, rather than a whole cache line,
with short term caching of only 4 entries per core and invalidation of the texture fetch cache on
a pipeline exception stall.
support of tile-ccnuma with on chip memory per tile.
I have done a research of whether it would be feasible to implement the heptane processor chip as a risc (true risc) ISA cpu.
I have found that in order to do so it needs to be nearly the exact opposite of the RISC-V ISA.
specification of the Anti-RiscV like ISA.
Pre release of the risky heptane ISA user mode subset v032024.1